ABSTRACT

This article describes the modeling and the results of the synthesis of a serial-parallel multiplier in a programmable logic device (PLD). The use of programmable logic devices allows modifications on the system and optimization on physical space in the project of digital circuits. Using the VHSIC Hardware Description Language (VHDL), the circuit could be described in logical units that were instantiated to compose the multiplier. A comparative analysis showing the occupied area of the component is presented, beyond the comparison with a combinational multiplier. Three circuits, with 4, 8 and 16 bits were analyzed, for which it was observed an almost linear growing in the occupied area of the component. The developed work is the initial study about digital multipliers, which will be used in the implementation of a Fast Fourier Transform (FFT) processor. This processor is part of a master dissertation about electroencephalographic signals analysis and pattern recognition.